The four MESI states
- Modified (M): this cache has the only valid copy and it is dirty relative to memory.
- Exclusive (E): this cache has the only copy, and it is clean.
- Shared (S): multiple caches may hold clean copies.
- Invalid (I): the cache line cannot be used as a valid copy.
A two-core example
Suppose Core 0 reads address X and no other core has it. Its line may enter Exclusive. Core 1 then reads X; the line can become Shared in both caches. If Core 0 wants to write X, it must obtain write ownership, causing other cached copies to be invalidated or otherwise transitioned according to the protocol. The exact transaction names and implementation vary by processor.
Coherence is not the same as consistency
Coherence concerns the order and visibility of operations to an individual memory location or cache line. Memory consistency defines which orderings of operations across locations are observable. Software still needs correct synchronization—atomics, locks, and memory-order rules—even on a coherent machine.
Where DMA fits
Do not assume a coherent CPU cache automatically means every DMA path is coherent. Some systems provide hardware-coherent I/O; others require OS DMA mapping and synchronization APIs. Follow the SoC and operating-system rules.
Interview-level takeaway
Be able to explain why a write needs exclusive ownership, how another core's copy is handled, and why coherence alone does not make a multi-step algorithm race-free. Real implementations may use MESI variants, directories, snoop filters, or other optimizations.
Final takeaway
Low-level engineering is about understanding the contract between hardware, firmware, and the operating system. Start with the specification, form a testable hypothesis, collect evidence, and validate behavior on the target platform.