Inter-processor interrupts
An IPI is a notification sent from one CPU to another. It can request rescheduling, run a callback, or signal that shared work is ready. An IPI is not itself a data transport: the payload is commonly represented by shared state or a platform-specific mechanism.
Hardware mailboxes
A mailbox peripheral may provide message registers, FIFO entries, interrupt generation, and sometimes ownership rules. It can be useful between heterogeneous cores or processors. Firmware must follow the hardware's acknowledgement, queue-depth, and interrupt-clearing semantics.
Shared memory
Shared memory carries the actual payload efficiently, but both sides need a protocol. Define ownership, message layout, sequence numbers, buffer lifetime, and what happens when a consumer is slow or restarts.
A robust message sequence
- Producer writes the payload into an agreed buffer.
- Producer applies required memory ordering or cache synchronization.
- Producer publishes a sequence/state flag.
- Producer notifies the consumer using an IPI or mailbox interrupt.
- Consumer validates sequence and payload before responding.
- Consumer publishes completion and the producer reuses the buffer only when safe.
Failure handling matters
For safety-oriented systems, include heartbeat timeouts, sequence validation, bounded retries, and a defined response to stale or malformed messages. A timeout can detect missing progress, but it does not prove why the peer failed. Avoid two cores concurrently writing the same shared fields without a synchronization design.
Cacheability, memory barriers, and interrupt-controller APIs are platform-specific. Validate the protocol on the actual hardware.
Final takeaway
Low-level engineering is about understanding the contract between hardware, firmware, and the operating system. Start with the specification, form a testable hypothesis, collect evidence, and validate behavior on the target platform.