BIOS vs. UEFI
Boot process, architecture, and key differences between legacy BIOS and modern UEFI.
Read article ↗ TECHNICAL NOTES · REAL EXPERIMENTS
Technical Notes on
Embedded Systems
Practical guides. Real experiments. Clear explanations.
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Armv7-A vs. Armv8-A: AArch32 and AArch64
Compare registers, instruction sets, exception levels, MMU setup, and boot-time implications.
Read article ↗MBR vs. GPT: How Bootloaders Start
Understand partition tables, BIOS and UEFI boot paths, and where the bootloader fits.
Read article ↗DMA and Cache Coherency
Why a CPU and DMA device can see different data, and how cache maintenance helps.
Read article ↗NOR vs. NAND Flash
Read access, erase behavior, XIP, and where each flash technology fits.
Read article ↗static int demo_probe(struct device *dev)
{
dev_info(dev, "device ready");
return 0;
}What Happens When a Linux Driver Probes?
Follow device matching, resource setup, and the driver's probe callback.
Read article ↗Interrupts vs. Polling vs. DMA
Compare CPU overhead, latency, and when each hardware interaction model makes sense.
Read article ↗driver → hardware
trace · debug · validateDevice Tree: How Linux Describes Hardware
Follow compatible strings, resources, and the path from DTS to a driver's probe callback.
Read article ↗driver → hardware
trace · debug · validatePlatform, I²C, and SPI Drivers
Understand how Linux bus models affect matching, resource access, and driver design.
Read article ↗driver → hardware
trace · debug · validateProcess Context vs. Hard IRQ Context
Learn what can sleep, why interrupt handlers must stay short, and how to defer work.
Read article ↗driver → hardware
trace · debug · validateFrom open() to read(): A Character Driver Walkthrough
Trace a userspace system call through the VFS to a driver's file_operations callback.
Read article ↗driver → hardware
trace · debug · validateDesigning a Robust ioctl Interface
Build maintainable kernel/userspace commands with validation, stable structures, and compat in mind.
Read article ↗MESI Cache Coherence Explained
See how multicore CPUs manage cached copies—and why coherence is not the same as consistency.
Read article ↗SMP Communication: IPIs and Shared Memory
Compare notification and data exchange mechanisms for coordinating processor cores.
Read article ↗PCIe Bring-Up: A Debugging Checklist
Work from link training and enumeration to BAR assignment and realistic performance measurements.
Read article ↗From Reset Vector to Kernel Entry
Follow early firmware stages and the architecture-specific contract at kernel handoff.
Read article ↗ FROM THE WORKBENCH
Learn by tracing.
Build by testing.
Low-level concepts become clearer when you connect the theory to real hardware, logs, waveforms, and code. This is a growing collection of notes from that process.
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↓Drivers · BSP · Firmware
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ABOUT LOWLEVEL LABS
Curiosity below the abstraction.
LowLevel Labs is a technical knowledge space for embedded software, Linux internals, firmware, processor architecture, and hands-on debugging. The goal is simple: explain how systems work beneath the APIs—and share practical notes that help engineers reason from hardware to software.
UNDERSTAND · EXPERIMENT · DOCUMENT